1. Field of the Invention
The present invention relates to a method for receiving data in the high-speed synchronous communication among LSIs.
2. Description of the Related Art
Heretofore, in wireless communication systems, techniques have been developed to optimize a timing to sample data from a baseband received signal. For example, Japanese Patent Application Publication No. 2003-333020 discloses a receiving circuit for a baseband received signal which properly restores a symbol in the baseband received signal (serial signal). One example of this technique is based on the Bluetooth standard with a synchronous word of 64 bits. In other words, the receiving circuit determines the optimum phase on the basis of a detection result of each of the 64-bit synchronous words.
FIG. 8 is a schematic block diagram showing a configuration example of the conventional synchronous circuit. A baseband signal is sampled in a synchronous-word detection circuit 7p with frequency equal to an m-fold (m is an integer of 2 or larger) transmission rate. Here, the synchronous words are added to the head of the baseband signal. In other words, the synchronous-word detection circuit 7p compares the synchronous word included in each of m phases (1 symbol) of the baseband signal with the expected value. Then, one of the m phases including the largest number of the bits coinciding with the expected value is transmitted as the optimum phase to the frequency drift correcting circuit 5p. A FIFO buffer 6p uses this optimum phase to output a stable received symbol to the internal circuit. Thus, the synchronous-word detection circuit 7p detects the optimum phase on the basis of how many symbols in the synchronous word coincide with the expected value.
The accuracy in the optimum phase detection can be improved by setting a range in the frame for a phase comparison to be as broad as possible. Accordingly, the technique disclosed in Japanese Patent Application Publication No. 2003-333020 is effective means in the case where the frame includes a high ratio of the synchronous words, or the synchronous words are disposed dispersedly in the frame.
However, when the synchronous word is added to the top of the baseband signal, incorrect data may be retained at the optimum phase which is determined on the basis of how many symbols in the synchronous words coincide with the expected value. This is because the center phase is shifted while the subsequent data such as payload is being received. It can be considered that this tendency is observed more often when, in particular, the bit number of the synchronous words at the header portion is small and a data length is long.
FIG. 9 is a diagram showing the conventional technique in which a sampling clock is selected from the jitter component of a frame. In FIG. 9, the baseband signals are sampled with the frequency that is 8 times as much as the transmission rate. In other words, each phase is shown as #0 to #7 by using the sampling clock of 8 phases per symbol. In addition, in FIG. 9, the conventional technique is based on a frame standard in which: a synchronous word with a small bit-width is added to a frame header portion; and the data length (payload data length) is long. Here, the jitter component at a symbol boundary of the synchronous word is assumed to occur in the phase #6, which is shown by the reference numerals 91a and 91b. The jitter component of the entire frame including data is spread wider than the jitter component detected in the synchronous word detection, and the jitter components occur in the phases #6, #7, #0, #1, and #2, which are shown by 92a and 92b. If coincidence between the synchronous word and the expected value is not detected only in the phase of #6 due to the jitter component, the most remote phase from the phase of #6, for example, the phase of #2 that is positioned 4 phases away therefrom (the arrow 93) is determined as a sampling clock suitable for the later data detection. On the other hand, when the entire frame is taken into consideration, the jitter components are so widely spread that incorrect data may be retained over the 5 phases of #6, #7, #0, #1 and #2. At this time, the phase (phase #2) determined as the optimum phase by the synchronous word detection may be determined as a boundary of the symbol when viewed as the entire frame, and this may cause incorrect data to be retained. For this reason, the phase selection needs to be made in consideration of how the jitter components are spread in the entire frame. In the case of FIG. 9, the phase #4 shown by the arrow 94 is a phase to be really obtained.
As shown in FIG. 9 as an example, in the prior art, the sampling clock (the phase #2 shown by the arrow 93) is determined based on a part of the jitter components (the reference numeral 91a, 91b). As a result, the optimum phase (the phase #4 shown by the arrow 94) based on the jitter components (the reference numeral 92a, 92b) of the entire frame fails to be selected. Accordingly, occurrence frequency of such a phenomenon that an incorrect phase is selected as the optimum phase is expected to increase when the bit number of the synchronous word of the header portion in one frame is small and the data length of the frame is long, i.e., when the ratio of the synchronous word to the frame is low. In addition, along with speeding-up of a transmission rate in recent years, the occurrence frequency is also expected to increase due to the growing ratio of jitter components per symbol.
As described above, there has been a need to improve accuracy of data sampling even when the ratio of synchronous words to a frame is low.